Abstract: Dynamic Flip-Flop Conversion (DFFC) is a time bor-rowing method for improving the performance of digital circuits. Existing types of DFFC [11], [12] suffer from successive critical and critical feedback paths that are frequently seen in digital circuits. Moreover, they are unable to increase the performance of the designs with short sequential depth. In this paper, we introduce a hybrid technique which utilizes DFFC together with a dynamic clock stretching mechanism. Our technique is able to mitigate the problems of successive critical and critical feedback path structures even in the presence of process variations. The results show that our hybrid technique is able to increase the performance of some ITC’99 and ISCAS’89 benchmarks by 24.4% on average while DFFC Type C increases the performance only by 8.4% on average. Furthermore, we have shown that our hybrid technique is able to tolerate process variations, 18% power supply variation, and 100 ?C temperature variations, 27.3%, 16.4%, and 13.3% better than the state-of-the-art methods on average, respectively.

Keywords: Dynamic flip-flop conversion, hold time violation (HTV), process variation, setup time violation (STV), time borrow-ing, transparency window.